HYS64T128020EML-3S-B Datasheet, PDF (25/39 Pages) Qimonda AG – 214-Pin Unbuffered DDR2 SDRAM MicroDIMM Modules Low Power

Preliminary Internet Data Sheet
HYS64T128020EML-[3S/3.7/5]-B
Unbuffered DDR2 SDRAM MicroDIMM Modules
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
Symbol
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-667& DDR2-800
Parameter / Condition
Values
Unit
Note
Min.
Max.
t_AOND
ODT turn-on delay
2
2
n_CK
1)
t_AON
ODT turn-on
t_AC.MIN
t_AC.MAX + 0.7 ns
ns
1)2)
t_AONPD
ODT turn-on (Power-Down Modes)
t_AC.MIN + 2 ns 2 t_{CK +} t_AC.MAX + 1 ns
ns
1)
t_AOFD
ODT turn-off delay
2.5
2.5
n_CK
1)
t_AOF
ODT turn-off
t_AC.MIN
t_AC.MAX + 0.6 ns
ns
1)3)
t_AOFPD
ODT turn-off (Power-Down Modes)
t_AC.MIN + 2 ns 2.5 t_{CK +} t_AC.MAX + 1 ns ns
1)
t_ANPD
ODT to Power Down Mode Entry Latency
3
—
n_CK
1)
t_AXPD
ODT Power Down Exit Latency
8
—
n_CK
1)
1) New units, “t_CK.AVG” and “n_CK”, are introduced in DDR2-667 and DDR2-800. Unit “t_CK.AVG” represents the actual t_CK.AVG of the input clock
under operation. Unit “n_CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “t_CK” is used for both concepts. Example: t_XP = 2 [n_CK] means; if Power Down exit is registered at T_m, an Active command may
be registered at T_m + 2, even if (T_m + 2 - T_m) is 2 x t_CK.AVG + t_{ERR.2PER(Min)}.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-667/800, t_AOND is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if t_CK(avg) = 3 ns is assumed, t_AOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
Rev. 0.5, 2007-05
25
05212007-7F24-MITO