HYS64T128020EML-3S-B Datasheet, PDF (5/39 Pages) Qimonda AG – 214-Pin Unbuffered DDR2 SDRAM MicroDIMM Modules Low Power

Preliminary Internet Data Sheet
HYS64T128020EML-[3S/3.7/5]-B
Unbuffered DDR2 SDRAM MicroDIMM Modules
2
Pin Configuration and Block Diagrams
This chapter contains the pin configuration and block diagrams.
2.1
Pin Configuration
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 4 (214 pins). The abbreviations used in
columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Figure 1.
Ball No.
Name
Clock Signals
122
CK0
194
CK1
123
CK0
195
CK1
43
CKE0
147
CKE1
NC
Control Signals
165
S0
62
S1
NC
163
RAS
60
CAS
56
WE
Address Signals
55
BA0
162
BA1
Pin
Type
Buffer
Type
Function
TABLE 4
Pin Configuration of MDIMM
I
SSTL
Clock Signal CK 1:0, Complementary Clock Signal CK 1:0
I
SSTL
Note: The system clock inputs. All address and command lines are
I
SSTL
I
SSTL
sampled on the cross point of the rising edge of CK and the falling
edge of CK. A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized
to the input clock.
I
SSTL
Clock Enables 1:0
I
SSTL
Note: Activates the DDR2 SDRAM CK signal when HIGH and
deactivates the CK signal when LOW. By deactivating the clocks,
CKE0 initiates the Power Down Mode or the Self Refresh Mode.
1. 2-rank module
NC
Not Connected
Note: 1-rank module
I
SSTL
Chip Select Rank 1:0¹⁾²⁾
I
SSTL
NC
Not Connected
Note: 1-rank module
I
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
I
SSTL
Enable (WE)
I
SSTL
Note: When sampled at the cross point of the rising edge of CK,and
falling edge of CK, RAS, CAS and WE define the operation to be
executed by the SDRAM.
I
SSTL
Bank Address Bus 1:0
I
SSTL
Note: Select internal SDRAM memory bank
Rev. 0.5, 2007-05
5
05212007-7F24-MITO