HYS64T128020EML-3S-B Datasheet, PDF (10/39 Pages) Qimonda AG – 214-Pin Unbuffered DDR2 SDRAM MicroDIMM Modules Low Power

Preliminary Internet Data Sheet
HYS64T128020EML-[3S/3.7/5]-B
Unbuffered DDR2 SDRAM MicroDIMM Modules
1) Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the
command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected
by S1. The input signals also disable all outputs (except CKE and ODT) of the register(d) on the DIMM when both inputs are high. When
S is HIGH, all register outputs (except CK, ODT and Chip select) remain in the previous state.
2) 2-rank module
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 5
Abbreviations for Pin Type
Abbreviation
SSTL
CMOS
OD
TABLE 6
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 0.5, 2007-05
10
05212007-7F24-MITO