HYS72T512022EP Datasheet, PDF (5/36 Pages) Qimonda AG – 240-Pin Dual Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
2
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 4 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 5
and Table 6 respectively. The pin numbering is depicted in
Figure 1.
Ball No.
Name
Clock Signals
185
186
52
171
CK0
CK0
CKE0
CKE1
NC
Control Signals
193
S0
76
S1
NC
192
74
73
18
Address Signals
71
190
54
RAS
CAS
WE
RESET
BA0
BA1
BA2
NC
Pin Buffer Function
Type Type
TABLE 4
Pin Configuration of RDIMM
I
SSTL Clock Signal CK0, Complementary Clock Signal CK0
I
SSTL
I
SSTL Clock Enables 1:0
I
SSTL ^{Note: 2-Ranks module}
NC —
Not Connected
Note: 1-Rank module
I
SSTL Chip Select Rank 1:0
I
SSTL ^{Note: 2-Ranks module}
NC —
Not Connected
Note: 1-Rank module
I
SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write
I
SSTL ^{Enable (WE)}
I
SSTL
I
CMOS Register Reset
I
SSTL Bank Address Bus 1:0
I
SSTL
I
SSTL Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
I
SSTL Not Connected
Less than 1Gb DDR2 SDRAMS
Rev. 1.0, 2007-03
5
03292007-RHOW-C5L6