HYS72T512022EP Datasheet, PDF (17/36 Pages) Qimonda AG – 240-Pin Dual Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
3.3.2
Component AC Timing Parameters
Timing Parameters: Table 13 for DDR2–667D, Table 14 for DDR2–533C
TABLE 13
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Min.
Max.
Unit
Note^{1)2)3)4)5)6)7)}
8)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
t_AC
t_CCD
t_CH.AVG
t_CK.AVG
t_CKE
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_CL.AVG
t_DAL
t_DELAY
DQ and DM input hold time
t_DH.BASE
DQ and DM input pulse width for each input
t_DIPW
DQS output access time from CK / CK
t_DQSCK
DQS input high pulse width
t_DQSH
DQS input low pulse width
t_DQSL
DQS-DQ skew for DQS & associated DQ signals t_DQSQ
DQS latching rising transition to associated clock t_DQSS
edges
DQ and DM input setup time
t_DS.BASE
DQS falling edge hold time from CK
t_DSH
DQS falling edge to CK setup time
t_DSS
Four Activate Window for 1KB page size products t_FAW
Four Activate Window for 2KB page size products t_FAW
CK half pulse width
t_HP
Data-out high-impedance time from CK / CK
t_HZ
Address and control input hold time
t_IH.BASE
Control & address input pulse width for each input t_IPW
Address and control input setup time
t_IS.BASE
DQ low impedance time from CK/CK
t_LZ.DQ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
MRS command to ODT update delay
t_MOD
Mode register set command cycle time
t_MRD
OCD drive mode output delay
t_OIT
DQ/DQS output hold time from DQS
t_QH
–450
2
0.48
3000
3
+450
—
0.52
8000
—
0.48
WR + t_nRP
t_IS + t_{CK .AVG} +
t_IH
175
0.35
–400
0.35
0.35
—
– 0.25
0.52
—
––
––
—
+400
—
—
240
+ 0.25
100
0.2
0.2
37.5
50
Min (t_CH.ABS,
t_CL.ABS)
—
275
0.6
200
2 x t_AC.MIN
t_AC.MIN
0
2
0
t_HP – t_QHS
––
—
—
—
—
__
t_AC.MAX
—
—
—
t_AC.MAX
t_AC.MAX
12
—
12
—
ps
nCK
t_CK.AVG
ps
nCK
9)
—
10)11)
—
12)
t_CK.AVG
nCK
ns
10)11)
13)14)
ps
t_CK.AVG
ps
t_CK.AVG
t_CK.AVG
ps
t_CK.AVG
19)20)15)
—
9)
—
—
16)
17)
ps
t_CK.AVG
t_CK.AVG
ns
ns
ps
18)19)20)
17)
17)
31)
31)
21)
ps
ps
t_CK.AVG
ps
ps
ps
ns
nCK
ns
ps
9)22)
25)23)
—
24)25)
9)22)
9)22)
1)
—
1)
26)
Rev. 1.0, 2007-03
17
03292007-RHOW-C5L6