HYS72T512022EP Datasheet, PDF (18/36 Pages) Qimonda AG – 240-Pin Dual Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
Parameter
Symbol
DDR2–667
Min.
Max.
Unit
Note^{1)2)3)4)5)6)7)}
8)
DQ hold skew factor
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Active to active command period for 2KB page
size products
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
t_QHS
t_RPRE
t_RPST
t_RRD
t_RRD
t_RTP
t_WPRE
t_WPST
t_WR
t_WTR
t_XARD
t_XARDS
—
340
0.9
1.1
0.4
0.6
7.5
—
10
—
7.5
—
0.35
—
0.4
0.6
15
—
7.5
—
2
—
7 – AL
—
ps
t_CK.AVG
t_CK.AVG
ns
27)
28)29)
28)30)
31)
ns
31)
ns
t_CK.AVG
t_CK.AVG
ns
ns
nCK
nCK
31)
—
—
31)
31)32)
—
—
Exit precharge power-down to any valid
t_XP
2
command (other than NOP or Deselect)
—
nCK —
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
t_XSNR
t_XSRD
WL
t_RFC +10
—
200
—
RL–1
ns
31)
nCK —
nCK —
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
7) The output timing reference voltage level is V_TT.
8) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG + t_{ERR.2PER(Min)}.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN} = – 272
ps and t_{ERR(6- 10PER).MAX} = + 293 ps, then t_{DQSCK.MIN(DERATED)} = t_DQSCK.MIN – t_{ERR(6-10PER).MAX} = – 400 ps – 293 ps = – 693 ps and
t_{DQSCK.MAX(DERATED)} = t_DQSCK.MAX – t_{ERR(6-10PER).MIN} = 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQ for DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}
= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)} = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12) t_CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of t_IS + 2 x t_CK + t_IH.
Rev. 1.0, 2007-03
18
03292007-RHOW-C5L6