HYB25D256800CE Datasheet, PDF (32/39 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Symbol –5
–6
TABLE 23
I_DD Specification
–7
Unit Note/Test Condition¹⁾
DDR400B
DDR333
DDR266A
Typ.
Max.
Typ.
Max.
Typ.
Max.
I_DD0
70
90
60
75
50
65
mA ×4/×8²⁾³⁾
75
90
65
75
55
65
mA ×16 ³⁾
I_DD1
80
100
70
85
65
75
mA ×4/×8 ³⁾
95
110
80
95
70
85
mA ×16 ³⁾
I_DD2P
4
5
4
5
3
4
mA ³⁾
I_DD2F
30
36
25
30
20
24
mA ³⁾
I_DD2Q
20
28
17
24
15
21
mA ³⁾
I_DD3P
13
18
11
15
9
13
mA ³⁾
I_DD3N
38
45
32
38
28
36
mA ³⁾
43
54
36
45
30
40
mA ×16 ³⁾
I_DD4R
85
100
70
100
120
85
85
60
100
70
70
mA ×4/×8 ³⁾
85
mA ×16 ³⁾
I_DD4W
90
105
75
100
130
90
90
65
110
75
75
mA ×4/×8 ³⁾
90
mA ×16 ³⁾
I_DD5
140
I_DD6
1.4
—
190
3.0
—
120
1.4
—
160
3.0
1.5
100
1.4
—
140
3.0
—
mA ³⁾
mA ⁴⁾
mA Low power⁵⁾
I_DD7
210
250
180
215
140
170
mA ×4/×8 ³⁾
210
250
180
215
140
170
mA ×16 ³⁾
1) Test conditions for typical values: V_DD = 2.5 V (DDR333), V_DD = 2.6 V (DDR400), T_A = 25 °C, test conditions for maximum values:
V_DD = 2.7 V, T_A = 10 °C
2) I_DD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and
200 MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
5) Low power available on request
Rev. 2.3, 2007-03
32
03062006-8CCM-VPUW