HYB25D256800CE Datasheet, PDF (28/39 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Parameter
Symbol –5
DDR400B
–6
DDR333
Unit Note/ Test
Condition¹⁾
Min.
Max. Min.
Max.
Internal write to read command t_WTR
2
delay
—
1
—
t_CK
2)3)4)5)
Exit self-refresh to non-read
command
t_XSNR
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read command t_XSRD
200
—
200
—
t_CK
2)3)4)5)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual systemclock cycle time.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_IH(ac) and V_IL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on t_DQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Parameter
TABLE 21
AC Timing - Absolute Specifications for PC2700
Symbol –7
DDR266A
Unit Note/Test
Condition¹⁾
Min.
Max.
DQ output access time from CK/CK
CK high-level width
Clock cycle time
t_AC
–0.75
t_CH
0.45
t_CK
7.5
7.5
+0.75
0.55
12
12
ns
2)3)4)5)
t_CK
2)3)4)5)
ns
CL = 3.0 ³⁾⁴⁾⁵⁾
ns
CL = 2.5 ^2)3)4)5)
7.5
12
ns
CL = 2.0 ^2)3)4)5)
CK low-level width
t_CL
0.45
0.55
t_CK
2)3)4)5)
Auto precharge write recovery + precharge time t_DAL
(t_WR/t_CK)+(t_RP/t_CK)
—
t_CK
2)3)4)5)6)
DQ and DM input hold time
t_DH
0.5
—
ns
2)3)4)5)
DQ and DM input pulse width (each input)
t_DIPW
1.75
—
ns
2)3)4)5)6)
DQS output access time from CK/CK
t_DQSCK –0.75
+0.75
ns
2)3)4)5)
DQS input low (high) pulse width (write cycle) t_DQSL,H 0.35
—
t_CK
2)3)4)5)
Rev. 2.3, 2007-03
28
03062006-8CCM-VPUW