HYB25D256800CE Datasheet, PDF (23/39 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
TABLE 17
Input and Output Capacitances
Parameter
Symbol
Min.
Values
Unit
Typ. Max.
Note/
Test Condition
Input Capacitance: CK, CK
C_I1
Delta Input Capacitance
C_dI1
Input Capacitance: All other input-only pins C_I2
Delta Input Capacitance: All other input-only C_dIO
pins
1.5
—
2.0
—
—
—
1.5
—
2.0
—
—
—
2.5
pF
3.0
pF
0.25 pF
2.5
pF
3.0
pF
0.5
pF
P-TFBGA-60-12¹⁾
P-TSOPII-66 ¹⁾
1)
P-TFBGA-60-12 ¹⁾
P-TSOPII-66 ¹⁾
1)
Input/Output Capacitance: DQ, DQS, DM C_IO
3.5
—
4.5
pF
P-TFBGA-60-12
P-TFBGA-60-12 ¹⁾²⁾
4.0
—
5.0
pF
P-TSOPII-66 ¹⁾²⁾
Delta Input/Output Capacitance: DQ, DQS, C_dIO
DM
—
—
0.5
pF
1)
1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only. V_DDQ = V_DD =
2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C, V_OUT(DC) = V_DDQ/2, V_OUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
Rev. 2.3, 2007-03
23
03062006-8CCM-VPUW