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HYB25D256800CE Datasheet, PDF (26/39 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SDRAM
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
TABLE 19
AC Operating Conditions
Parameter
Symbol
Min.
Values
Max.
Unit Note1)/
Test
Condition
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31 —
V
—
VREF – 0.31 V
0.7
VDDQ + 0.6 V
0.5 × VDDQ– 0.5 × VDDQ+ V
0.2
0.2
2)3)
2)3)
2)3)4)
2)3)5)
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400); 0 °C ≤ TA ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
Parameter
Symbol
TABLE 20
AC Timing - Absolute Specifications for PC3200 and PC2700
–5
DDR400B
–6
DDR333
Unit Note/ Test
Condition1)
DQ output access time from
tAC
CK/CK
CK high-level width
tCH
Clock cycle time
tCK
CK low-level width
Auto precharge write recovery +
precharge time
DQ and DM input hold time
DQ and DM input pulse width
(each input)
DQS output access time from
CK/CK
DQS input low (high) pulse width
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1st DQS
latching transition
DQ and DM input setup time
tCL
tDAL
tDH
tDIPW
tDQSCK
tDQSL,H
tDQSQ
tDQSS
tDS
Min.
–0.5
Max.
+0.5
0.45
0.55
5
8
6
12
7.5
12
0.45
0.55
(tWR/tCK)+(tRP/tCK)
0.4
—
1.75
—
–0.6
+0.6
0.35
—
—
+0.40
0.72
1.25
0.4
—
Min.
–0.7
0.45
6
6
7.5
0.45
0.45
1.75
–0.6
0.35
—
0.75
0.45
Max.
+0.7
ns
2)3)4)5)
0.55
12
12
12
0.55
—
—
tCK
2)3)4)5)
ns CL = 3.0 3)4)5)
ns CL = 2.5 2)3)4)5)
ns CL = 2.0 2)3)4)5)
tCK
2)3)4)5)
tCK
2)3)4)5)6)
ns
2)3)4)5)
ns
2)3)4)5)6)
+0.6
ns
2)3)4)5)
—
tCK
2)3)4)5)
+0.40 ns TFBGA 2)3)4)5)
1.25
—
tCK
2)3)4)5)
ns
2)3)4)5)
Rev. 2.3, 2007-03
26
03062006-8CCM-VPUW
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