HYB25D256800CE Datasheet, PDF (18/39 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Current State CKE n-1
CKEn
Command n
TABLE 12
Truth Table 2: Clock Enable (CKE)
Action n
Note
Previous Cycle Current Cycle
Self Refresh L
Self Refresh L
L
X
Maintain Self-Refresh
1)
H
Deselect or NOP
Exit Self-Refresh
2)
Power Down L
L
X
Maintain Power-Down
Power Down L
H
Deselect or NOP
Exit Power-Down
All Banks Idle H
L
Deselect or NOP
Precharge Power-Down Entry
All Banks Idle H
L
AUTO REFRESH
Self Refresh Entry
Bank(s) Active H
L
Deselect or NOP
Active Power-Down Entry
—
H
H
See Table 13
—
1) V_REF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t_XSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 2.3, 2007-03
18
03062006-8CCM-VPUW