HYB39SC256 Datasheet, PDF (3/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM

Internet Data Sheet
1
Overview
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
This chapter lists all main features of the product family HY[B/I]39SC256[80/16]0F[E/F] and the ordering information.
1.1
Features
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C Operating Temperature for HYB...
• -40 to 85 °C Operating Temperature for HYI...
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
• Data Mask for Read / Write control (x8, x16)
• Data Mask for Byte Control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 8192 refresh cycles / 64 ms (7.8 µs)
• Random Column Address every CLK (1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface
• Plastic Packages
– PG-TSOPII-54 (400mil width)
– PG-TFBGA-54 (12 mm x 8 mm)
• RoHS compliant product
Product Type Speed Code
Speed Grade
–6
PC166–333
Max. Clock Frequency
1) Max. Frequency CL/t_RCD / t_RP
@CL3
@CL2
f_CK3 166
t_CK3 6
t_AC3 5.4
t_CK2 7.5
t_AC2 5.4
–7
PC143–333
PC133–222¹⁾
143
7
5.4
7.5
5.4
TABLE 1
Performance
Unit
—
MHz
ns
ns
ns
ns
Rev. 1.25, 2007-06
3
03062006-NMGU-CQ9D