HYB39SC256 Datasheet, PDF (17/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
Parameter
Symbol
–7
–6
Unit Note¹⁾²⁾³⁾
PC143–333
PC166–333
Min. Max. Min. Max.
Write Cycle
Last Data Input to Precharge
(Write without Auto Precharge)
t_WR
14 —
12
—
ns
8)
Last Data Input to Activate
(Write with Auto Precharge)
t_DAL(min.)
—
—
—
—
t_CK
9)
DQM Write Mask Latency
t_DQW
0
—
0
—
t_CK
1) T_A = 0 to 70 °C; V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V, t_T = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between V_IH and V_IL. All AC measurements assume t_T = 1 ns with the AC output load circuit shown in figure below.
Specified t_AC and t_OH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (t_T/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock t_ac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time t_oh is 1.8 ns for PC133 components with no termination and 0 pF load.
6) If t_T is longer than 1 ns, a time (t_T - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-
Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times t_CK greater
or equal the specified t_WR value, where t_ck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of t_DAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. t_CK is equal to the actual system clock time.
CLO C K 1.4 V
t IS
t IH
tCH
2.4 V
0.4 V
tT
t_CL
IN PU T
OUTPUT
1.4 V
tAC
tLZ
tAC
tOH
tHZ
1.4 V
IO.vsd
FIGURE 4
Measurement conditions for t_AC and t_OH
I/O
50 pF
Measurement conditions for
t_AC and t_OH
Rev. 1.25, 2007-06
17
03062006-NMGU-CQ9D