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HYB39SC256 Datasheet, PDF (14/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
TABLE 8
DC Characteristics
Parameter
Symbol
Values
Min. Max.
Unit Note/
Test Condition
Supply Voltage
VDD
3.0 3.6
V
1)
I/O Supply Voltage
VDDQ 3.0 3.6
V
1)
Input high voltage
VIH
2.0 VDDQ + 0.3 V
1)2)
Input low voltage
VIL
–0.3 +0.8
V
1)2)
Output high voltage (IOUT = – 4.0 mA)
VOH
2.4 —
V
1)
Output low voltage (IOUT = 4.0 mA)
VOL
— 0.4
V
1)
Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL
–5 +5
µA
Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ)
IOL
–5 +5
µA
1) All voltages are referenced to VSS
2) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
Parameter
TABLE 9
Input and Output Capacitances
Symbol Values
Unit Note
Min. Max.
Input Capacitances: CK
Input Capacitance
(A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
CI1
2.5 3.5
pF
1)2)
CI2
2.5 3.8
pF
1)2)
Input/Output Capacitance (DQ)
CI0
4.0 6.0
pF
1)2)
1) VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz, TA see Table 7
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
Parameter
Operating Current
Precharge Standby Current
No Operating Current
Burst Operating Current
Auto Refresh Current
Self Refresh Current
One bank active, Burst length = 1
Power down mode
Non-power down mode
Active state (max. 4 banks)
Read command cycling
Auto Refresh command cycling
Self Refresh Mode, CKE=0.2 V, tCK=infinity
TABLE 10
IDD Conditions
Symbol
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
IDD5
IDD6
Rev. 1.25, 2007-06
14
03062006-NMGU-CQ9D