HYB39SC256 Datasheet, PDF (11/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM

Internet Data Sheet
Field
BL
BT
CL
TM
WBL
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
%$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $
     :%/
70
&/
%7
%/
UHJDGGU
Z
Z
Z
Z
03%6
Bits
Type
[2:0]
w
3
[6:4]
[8:7]
9
[12:10]
Description
TABLE 5
Mode Register Definition (BA[1:0] = 00_B)
Burst Length
Number of sequential bits per DQ related to one read/write command, see Table 6
Note: All other bit combinations are RESERVED
000_B 1
001_B 2
010_B 4
011_B 8
111_B Full Page (Sequential burst type only)
Burst Type
0_B Sequential
1_B Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010_B 2
011_B 3
Test Mode
Note: All other bit combinations are RESERVED.
00_B Mode register set
Write Burst Length
0_B Burst write
1_B Single bit write
Reserved, set to zero
Rev. 1.25, 2007-06
11
03062006-NMGU-CQ9D