HYB39SC256 Datasheet, PDF (16/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM

Internet Data Sheet
4.2
AC Characteristics
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
Parameter
Clock and Clock Enable
Clock Frequency
Access Time from Clock
Clock High Pulse Width
Clock Low Pulse Width
Transition time
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Out Hold Time
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
Rev. 1.25, 2007-06
03062006-NMGU-CQ9D
Symbol
TABLE 12
AC Timing - Absolute Specifications
–7
–6
Unit Note¹⁾²⁾³⁾
PC143–333
PC166–333
Min. Max. Min. Max.
t_CK
t_AC
t_CH
t_CL
t_T
t_IS
t_IH
t_CKS
t_CKH
t_RSC
t_SB
t_RCD
t_RP
t_RAS
t_RC
t_RFC
t_RRD
t_CCD
t_REF
t_SREX
t_OH
t_LZ
t_HZ
t_DQZ
7
—
7.5 —
—
5.4
—
5.4
2.5 —
2.5 —
0.3 1.2
6
—
7.5 —
—
5.4
—
5.4
2
—
2
—
0.3 1.2
ns CL3
ns CL2
ns CL3
ns CL2
3)4)5)
ns
ns
ns
1.5 —
0.8 —
1.5 —
0.8 —
2
—
0
7
1.5 —
0.8 —
1.5 —
0.8 —
2
—
0
6
ns
6)
ns
6)
ns
6)
ns
6)
t_CK
ns
15 —
15
15 —
15
37 100k 36
60 —
60
63 —
60
14 —
12
1
—
1
—
ns
7)
—
ns
7)
100k ns
7)
—
ns
7)
—
ns
—
ns
7)
—
t_CK
–
64
–
64
ms
1
—
3
—
1
—
2.5 —
t_CK
ns
3)5)
0
—
3
7
—
2
0
—
ns
3
6
ns
—
2
t_CK
16