HYB39SC256 Datasheet, PDF (2/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
HYB39SC256[80/16]0FE, HYI39SC256[80/16]0FF
Revision History: 2007-06, Rev. 1.25
Page
Subjects (major changes since last revision)
All
Adapted internet edition
41
Corrected in figure 28 (auto refresh) tRC to tRFC
Previous Revision: 2007-06, Rev. 1.24
8
Corrected figure 1
11,12
Corrected block diagram
Previous Revision: 2007-06, Rev. 1.23
18
Added text for Auto Refresh Command (CBR)
Previous Revision: 2007-06, Rev. 1.22
6
Corrected ball DQ0 to 2,8A for data signals x16 organization
6
Corrected data Data Signal Bus [7:0] for data signals x8 organization
Previous Revision: 2007-06, Rev. 1.21
13
Corrected operation command "Power Down / Clock suspend ...” in truth table
Previous Revision: 2007-05, Rev. 1.2
13
Corrected operation command "Power Down Exit" to X (WE#)
15
Corrected text to "After the mode register is set a NOP command is required" , chapter 3.2
19
Corrected text to "One clock delay is required for mode entry and exit", chapter 3.4
21
Corrected the line "Input Capacitances: CK" in table 10, chapter 4
21
Corrected to A0-A12 in table 10, chapter 4
22
Corrected tCK MIN in table 13
22
Corrected CLE setup time in table 13
Previous Revision: 2007-05, Rev. 1.11
6
Corrected A6 position from H to 3H in table 3
Previous Revision: 2006-09, Rev. 1.1
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21
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03062006-NMGU-CQ9D