English
Language : 

HYB39SC256 Datasheet, PDF (15/24 Pages) Qimonda AG – 256-MBit Synchronous DRAM
◁
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
Symbol
Test Condition
TABLE 11
IDD Specifications and Conditions
–6
–7
Unit
Note 1)
IDD1
IDD2P
IDD2N
tRC = tRC(min), IO = 0 mA
CS =VIH (min.), CKE ≤VIL(max)
CS =VIH (min.), CKE≥ VIH(min)
100
80
mA
2)3)
2
2
mA
1)
26
22
mA
1)
IDD3N
IDD3P
IDD4
CS = VIH(min), CKE ≥VIH(min.)
CS = VIH(min), CKE ≤ VIL(max.)
—
40
35
mA
1)
5
5
mA
1)
65
57
mA
1)3)
IDD5
tRFC= tRFC(min)
168
142
mA
4)
tRFC= 15.6 µs
25
25
mA
IDD6
—
3
3
mA
1) VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, TA see Table 7
2) These parameters depend on the cycle rate. All values are measured at 133 MHz for -7 with the outputs open. Input signals are changed
once during tCK.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and
the VDDQ current is excluded.
4) tRFC= tRFC(min) “burst refresh”, tRFC= 15.6 µs “distributed refresh”.
Rev. 1.25, 2007-06
15
03062006-NMGU-CQ9D
 ▷