HYB25L256160AC Datasheet, PDF (3/18 Pages) Infineon Technologies AG – 256-Mbit Mobile-RAM

HY[B/E]25L256160A[F/C]–7.5
256MBit Mobile-RAM
Overview
1
Overview
1.1
Features
• 16 Mbits × 16 organisation
• Fully synchronous to positive clock edge
• Four internal banks for concurrent operation
• Data mask (DM) for byte control with write and read data
• Programmable CAS latency: 2 or 3
• Programmable burst length: 1, 2, 4, 8, or full page
• Programmable wrap sequence: sequential or interleaved
• Random column address every clock cycle (1-N rule)
• Deep power down mode
• Extended mode register for Mobile-RAM features
• Temperature compensated self refresh with on-die temperature sensor
• Partial array self refresh
• Power down and clock suspend mode
• Automatic and controlled precharge command
• Auto refresh mode (CBR)
• 8192 refresh cycles / 64 ms
• Self-refresh with programmble refresh period
• Programmable power reduction feature by partial array activation during self-refresh
• V_DDQ = 1.8V or 2.5 V or 3.3 V
• V_DD = 2.5 V or 3.3 V
• P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm²)
• Operating temperature range:
commercial (0 °C to +70 °C)
extended (–25 °C to +85 °C)
Table 1 Performance ¹⁾
Part Number Speed Code
max. Clock Frequency
@CL3
f_CK3
min. Clock Period
@CL3
t_CK3
min. Access Time from Clock
@CL3
t_AC3
min. Clock Period
@CL2
t_CK2
min. Access Time from Clock
@CL2
t_AC2
1) for VDDQ = 2.5 V or 3.3 V; see Table 9 for VDDQ dependent performance
–7.5
133
7.5
6.0
9.5
6.0
Unit
MHz
ns
ns
ns
ns
Internet Data Sheet
3
Rev. 1.41, 2006-12
04292004-EQNL-FLNW