HYB25L256160AC Datasheet, PDF (13/18 Pages) Infineon Technologies AG – 256-Mbit Mobile-RAM

HY[B/E]25L256160A[F/C]–7.5
256MBit Mobile-RAM
Electrical Characteristics
Table 9 AC Timing Characteristics¹⁾²⁾ (cont’d)
Parameter
Symbol
–7.5
Unit Note/ Test Condition
min. max.
Refresh Cycle
Refresh period
t_REF
—
64
ms
Self refresh exit time
t_SREX
1
—
t_CK
Read Cycle
Data output hold time
t_OH
3
—
ns
4)7)8)
Data output from high to low impedance
t_LZ
1
—
ns
Data output from low to high impedance
t_HZ
3
7
ns
DQM data output disable latency
t_DQZ
—
2
t_CK
Write Cycle
Write recovery time
t_WR
14
—
ns ⁹⁾
DQM write data mask latency
t_DQW
0
—
t_CK
1) 0 °C ≤ T_C ≤ 70 °C (comm.) and –25 °C ≤ T_CASE ≤ +85 °C; recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet.
3) Symbol index 2 and 3 refer to CL = 2 and CL = 3.
4) AC timing tests are referenced to the 0.9 V crossover point. The transition time is measured between V_IH and V_IL. All AC
measurements assume t_T = 1 ns with the AC output load circuit (details will be defined later). Specified t_AC and t_OH
parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1V/ns edge rate
(see Figure 2).
5) If clock rising time is longer than 1 ns, a time (t_T/2 - 0.5) ns has to be added to this parameter.
6) If t_T is longer than 1 ns, a time (t_T - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
8) Access time from clock t_AC is 4.6 ns for –7.5 components with no termination and 0 pF load,
Data out hold time t_OH is 1.8 ns for –7.5 components with no termination and 0 pF load.
9) The write recovery time of t_WR = 14 ns allows the use of one clock cycle for the write recovery time when the memory
operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock
cycles for t_WR are mandatory. QIMONDA recommends to use two clock cylces for the write recovery time in all applications.
I/O
30 pF
Figure 2 Measurement Conditions for t_AC and t_OH
Internet Data Sheet
13
Rev. 1.41, 2006-12
04292004-EQNL-FLNW