HYB18L128160BF Datasheet, PDF (3/55 Pages) Infineon Technologies AG – DRAMs for Mobile Applications

HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewFeatures
1
Overview
This chapter gives an overview of the DRAMs for Mobile Applications product family and describes its main
characteristics.
1.1
Features
The DRAMs for Mobile Applications offers the following key features:
General Features
• 4 banks × 2 Mbit × 16 organization
• Fully synchronous to positive clock edge
• Four internal banks for concurrent operation
• Programmable CAS latency: 2, 3
• Programmable burst length: 1, 2, 4, 8 or full page
• Programmable wrap sequence: sequential or interleaved
• Programmable drive strength
• Auto refresh and self refresh modes
• 4096 refresh cycles / 64 ms
• Auto precharge
• Commercial (0 °C to +70 °C) and extended (-25 °C to +85 °C) operating temperature range
• 54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
• Low supply voltages: V_DD = 1.70V to 1.95V, V_DDQ = 1.70V to 1.95V
• Optimized self refresh (I_DD6) and standby currents (I_DD2/I_DD3)
• Programmable Partial Array Self Refresh (PASR)
• Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
• Power-Down and Deep Power Down modes
Table 1 Performance
Part Number Speed Code
Speed Grade
Access Time (t_AC.max)
Clock Cycle Time (t_CK.min)
CL = 3
CL = 2
CL = 3
CL = 2
- 7.5
133
5.4
6.0
7.5
9.5
Unit
MHz
ns
ns
ns
ns
Table 2
Item
Banks
Rows
Columns
Memory Addressing Scheme
Addresses
BA0, BA1
A0 - A11
A0 - A8
Data Sheet
3
Rev. 1.71, 2007-01
05282004-NZNK-8T0D