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HYB18L128160BF Datasheet, PDF (20/55 Pages) Infineon Technologies AG – DRAMs for Mobile Applications
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HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
Table 11 Timing Parameters for READ
Parameter
Symbol
- 7.5
Units Notes
min.
max.
Access time from CLK
CL = 3 tAC
—
5.4
ns
—
CL = 2 tAC
—
6.0
ns
DQ low-impedance time from CLK
tLZ
1.0
—
ns
—
DQ high-impedance time from CLK
tHZ
3.0
7.0
ns
Data out hold time
tOH
2.5
–
ns
—
DQM to DQ High-Z delay (READ Commands)
tDQZ
—
2
tCK
—
ACTIVE to ACTIVE command period
tRC
67
—
ns
1)
ACTIVE to READ or WRITE delay
tRCD
19
—
ns
ACTIVE to PRECHARGE command period
tRAS
45
100k
ns
PRECHARGE command period
tRP
19
—
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
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Figure 13 Single READ Burst (CAS Latency = 2)
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Data Sheet
20
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
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