HYB25DC512800C Datasheet, PDF (29/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
4.2.1
Current Measurement Conditions
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
I_DD1: Operating Current: One Bank Operation
1. General test condition
a) Only one bank is accessed with t_RC,MIN.
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d) I_OUT = 0 mA.
2. Timing patterns
a) DDR333B (166 MHz, CL = 2.5): t_CK = 6 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 9 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
b) DDR400B (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 11 × t_CK, t_RAS = 8 × t_CK
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
I_DD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with t_RCMIN.
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d) I_OUT = 0 mA.
2. Timing patterns
a) DDR333B (166 MHz, CL = 2.5): t_CK = 6 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
b) DDR400B (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 *× t_CK, t_RAS = 8 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
Rev. 1.3, 2006-12
29
03292006-W2FE-ELDX