HYB25DC512800C Datasheet, PDF (12/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
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Field Bits Type¹⁾ Description
TABLE 6
Mode Register Definition
BL
[2:0] W
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
BT
3
CL
[6:4]
001_B 2
010_B 4
011_B 8
Burst Type
See Table 7 for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
MODE [12:7]
010_B 2
011_B 3
110_B 2.5
101_B 1.5
Note: CL = 1.5 for DDR200 components only
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 1.3, 2006-12
12
03292006-W2FE-ELDX