HYB25DC512800C Datasheet, PDF (27/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM

Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
Active Standby Current: one bank active; CS ≥ V_IHMIN; CKE ≥ V_IHMIN; t_RC = t_RASMAX; t_CK = t_CKMIN; DQ, DM and DQS I_DD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; t_CK = t_CKMIN; I_OUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; t_CK = t_CKMIN
Auto-Refresh Current: t_RC = t_RFCMIN, burst refresh
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; t_CK = t_CKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
I_DD4R
I_DD4W
I_DD5
I_DD6
I_DD7
Rev. 1.3, 2006-12
27
03292006-W2FE-ELDX