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| HYB25DC512800C Datasheet, PDF (28/35 Pages) Qimonda AG – 512-Mbit Double-Data-Rate SDRAM | |||
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Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
Symbol
â6
â5
Unit
Note1)
DDR333
DDR400B
IDD0
70
75
mA
85
90
mA
IDD1
80
85
mA
95
110
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
4.6
4.6
mA
25
30
mA
22
23
mA
15
16
mA
37
42
mA
40
45
mA
IDD4R
85
90
mA
115
135
mA
IDD4W
90
95
mA
120
135
mA
IDD5
175
190
mA
IDD6
5
5
mA
IDD7
205
230
mA
230
250
mA
1) Test conditions : VDD = 2.7 V, TA = 10 °C
2) IDD specifications are tested after the device is properly initialized and measured at 200 MHz.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
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3)
3)
3)
3)
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3)
4)
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TABLE 21
IDD Specification
Rev. 1.3, 2006-12
28
03292006-W2FE-ELDX
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