HYS72D64301 Datasheet, PDF (20/51 Pages) Qimonda AG – 184 - Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR–[5/6/7]–B
Registered DDR SDRAM Module
Parameter
Symbol –5
DDR400B
–6
DDR333
Unit Note/ Test
Condition¹⁾
Min.
Max. Min.
Max.
Data-out low-impedance time
t_LZ
from CK/CK
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
Mode register set command cycle t_MRD
2
time
—
2
—
t_CK
2)3)4)5)
DQ/DQS output hold time from t_QH
DQS
t_HP –t_QHS
—
t_HP –t_QHS
—
ns
2)3)4)5)
Data hold skew factor
t_QHS
—
Active to Autoprecharge delay t_RAP
t_RCD
Active to Precharge command t_RAS
40
Active to Active/Auto-refresh
t_RC
55
command period
+0.50 —
—
t_RCD
70E+3 42
—
60
+0.50 ns
—
ns
70E+3 ns
—
ns
TFBGA ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Read or Write delay
t_RCD
15
Average Periodic Refresh Interval t_REFI
—
Auto-refresh to Active/Auto-
t_RFC
65
refresh command period
—
18
7.8
—
—
72
—
ns
2)3)4)5)
7.8
µs
2)3)4)5)10)
—
ns
2)3)4)5)
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
t_RP
t_RPRE
t_RPST
t_RRD
15
0.9
0.40
10
—
18
1.1
0.9
0.60
0.40
—
12
—
1.1
0.60
—
ns
2)3)4)5)
t_CK
2)3)4)5)
t_CK
2)3)4)5)
ns
2)3)4)5)
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command
delay
t_WPRE
t_WPRES
t_WPST
t_WR
t_WTR
0.25
0
0.40
15
2
—
0.25
—
0
0.60
0.40
—
15
—
1
—
—
0.60
—
—
t_CK
2)3)4)5)
ns
2)3)4)5)11)
t_CK
2)3)4)5)12)
ns
2)3)4)5)
t_CK
2)3)4)5)
Exit self-refresh to non-read
command
t_XSNR
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read command t_XSRD
200
—
200
—
t_CK
2)3)4)5)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock cycle time.
7) t_HZHZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_IH(ac) and V_IL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.42, 2007-01
20
03292006-7CZA-YS85