HYS72D64301 Datasheet, PDF (11/51 Pages) Qimonda AG – 184 - Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxx[G/H]BR–[5/6/7]–B
Registered DDR SDRAM Module
Pin#
Name
Other Pins
82
9, 16, 17,
71, 75, 76,
90, 101,
102, 103,
113, 163,
173
V_DDID
NC
Pin
Buffer Function
Type Type
O
OD
NC
—
V_DD Identification
Not connected
Abbreviation
I
O
I/O
AI
PWR
GND
NU
NC
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Usable (JEDEC Standard)
Not Connected (JEDEC Standard)
TABLE 5
Abbrevations for Pin Type
Abbreviation
SSTL
LV-CMOS
CMOS
OD
TABLE 6
Abbrevations for Buffer Type
Description
Serial Stub Terminalted Logic (SSTL2)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and
tristate, and allows multiple devices to share as a wire-OR.
Density Organization
512 MB
1 GB
1 GB
2 GB
64M × 72
128M ×72
128M ×72
256M ×72
Memory
Ranks
1
1
2
2
SDRAMs
64M ×8
128M ×4
64M ×8
128M ×4
# of
SDRAMs
8
18
18
36
# of row/bank/
column bits
13/2/11
13/2/12
13/2/11
13/2/12
Refresh
TABLE 7
Address Format
Period Interval
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
Rev. 1.42, 2007-01
11
03292006-7CZA-YS85