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PACE1757M Datasheet, PDF (8/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM
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PACE 1757 M/ME
SIGNAL PROPAGATION DELAYS
Symbol
TC(BR)L
TC(BR)H
TBGV(C)
TC(BG)X
TC(BB)L
TC(BB)H
TBBV(C)
TC(BB)X
TC(BL)L
TC(BL)H
TBLV(C)
TC(BL)X(IN)
TC(ST)V
TC(ST)X
TC(SA)H
TC(SA)L
TSA L(IBA )X
TRA V(C)
TC(RA)X
TC(SDW)L
TC(SD)H
TFC(SDR)L
TIBDX(SDR)H
TSDWH(IBD)X
TSDL(SD)H(Write)
TRD(RD)X
TC(RD)X
TC(IBA )V
TFC(IBA)X
TIBDRV(C)
TC(IBD)X(Read)
TC(IBD)X(Write)
TFC(IBD)V
TC(SNW)
TFC(TGO)
TRSTL(DMA EN)L
TC(DME)
TFC(NPU)
TC(ER)
TRSTL(NPU)
TREQV(C)
TC(REQ)X
TFV(BB)H
TBBH(F)X
TIRV(C)
TC(IR)X
TRSTL(TRSTH)
TC(XX)Z
Description
BUS REQUEST
BUSGRANT - Setup
BUSGRANT - Hold
BUS BUSY
BUS BUSY - Setup
BUS BUSY - Hold
BUS LOCK
BUS LOCK - Setup
BUS LOCK - Hold
M/IO
R/W
AS0:AS3, AK0:AK3, D/I
M/IO, R/W, AS0:AS3, AK0:AK3, D/I
STRBA
Address Hold from STRBA(L)
RDYA - Setup
RDYA - Hold
STRBD
RDYD - Setup
RDYD - Hold
IB0:IB15
- Setup
- Hold
DATAVALID (OUT)
SNEW
TRIGO RST
DMA ENABLE
NORMAL POWER-UP
CLK TO MAJER (UNRCV ER)
RESET
CON REQ
LEVEL SENSITIVE FAULTS
IOL 1/2 INT. USR INT (0:5) - Setup
PWRDN INT, LEVEL SENSITIVE - HOLD
RESET PULSE WIDTH
CLK TO TRI-STATE
20 MHz
MIN MAX
33
33
5
5
25
25
5
5
30
30
5
5
30
30
25
0
22
22
5
5
5
22
22
22
0
30
40
5
5
30
0
5
5
0
30
30
30
40
40
40
60
50
0
10
5
5
0
10
25
22
30 MHz
MIN MAX
25
25
5
5
24
20
5
5
25
20
5
5
25
25
20
0
17
17
5
5
5
17
17
17
0
25
26
5
5
25
0
5
5
0
25
26
26
35
35
35
50
40
0
10
5
5
0
10
20
17
35 MHz
MIN MAX
22
22
5
5
22
18
5
5
23
19
5
5
23
23
20
0
16
16
5
5
5
16
16
16
0
21
23
5
5
23
0
5
5
0
23
24
24
33
33
33
47
35
0
10
5
5
0
10
18
15
40 MHz
MIN MAX
22
22
5
5
20
17
5
5
21
17
5
5
20
20
20
0
16
16
5
5
5
14
14
14
0
17
20
5
5
20
0
5
5
0
20
22
22
30
30
30
45
30
0
10
5
5
0
10
15
13
Note 1: Units = ns
Document # MICRO-10 REV B
Page 8 of 34
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