PACE1757M Datasheet, PDF (25/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM

PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
FAULTS AND FLAGS
Mnemonic
Name
Description
MEM PRT ER
Memory Protect Error
An active-LOW input generated by the MMU or BPU, or both, during
attempted writes to protected memory. It is sampled by the BUS BUSY
signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus
cycle). The error is generated in one of the following conditions: a
mismatch in the access keys in the MMU page, an access to an execution
protected page during instruction cycles, an access to a write protected
page during data cycles or an access to a page write protected by the
BPU.
MEM PAR ER
Memory Parity Error
An active LOW signal which is sampled by the BUS BUSY signal into bit
2 of the CPU's Fault Register. It signals an error on the Data Bus during
a memory cycle. Two detection modes can be selected by programming
the control register of the MMU/COMBO: EDAC mode (6 Hamming code
parity bits) or single bit parity mode (even or odd parity). The signal is
inactive when none of the above modes are selected (default after reset).
EXT ADR ER IN External Address
Error In
An active-LOW input sampled by the BUS BUSY signal into the CPU
Fault Register (bit 5 or 8) depending on the cycle (memory or I/O).
EXT ADR ER OUT External Address
Error Out
An active LOW output which signals to the CPU and memory interface
logic that an unimplemented memory or illegal I/O access has taken
place.
SYSFLT₀ -
SYSFLT₁
EX AD ER /
SING ERR
System Fault 0,
System Fault 1
Illegal Address Error /
Single Error
Asynchronous, positive edge sensitive inputs that set bit 7 (SYSFLT₀)
or bits 13 and 15 (SYSFLT₁) in the P1750A/AE Fault Register.
An active LOW output from the PIC indicating an illegal address error
when referencing memory or I/O. It becomes an active HIGH input called
SINGLE ERROR for handshaking with the P1753 when the PIC is
programmed to support EDAC. Default state after reset is high impedance.
WR PROT /
PROT FLAG
Write Protected /
Protection Flag
Either an active LOW output (WR PROT, following STRBD timing)
during legal memory write cycles when no protection occurs, or an active
high (PROT FLAG) signal indicating a protection error in a write cycle.
Either mode can be selected by programming the COMBO control
register. Default mode after reset is Write Protected.
ME PA ER /
RAMDIS
Memory Parity Error
An active LOW output indicating a Parity error when reading from
memory. It becomes an active HIGH output called RAM DISABLE for
handshaking with the P1753 when the PIC is programmed to support
EDAC.
TC
Terminal Count
An active HIGH output from the PIC indicating a bus time out or a
watchdog trigger.
Document # MICRO-10 REV B
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