PACE1757M Datasheet, PDF (29/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM

COMBO REGISTER MAP DEFINITIONS
CONTROL REGISTER (1F50/9F50)
(Default = 00C6H)
QR1
QR2
QR3
QR4
ODD
EEI
EED
EPR
SPD
WPT
EB1
EB2
EIO
GPT
DMX
DLP
Enable error detection/correction or parity
checking/generation for memory addresses
00000H-3FFFFH.
Enable error detection/correction or parity
checking/generation for memory addresses
40000H-7FFFFH
Enable error detection/correction or parity
checking/generation for memory addresses
80000H-BFFFFH.
Enable error detection/correction or parity
checking/generation for memory addresses
C0000H-FFFFFH.
Enable odd parity, 1 = ODD, 0 = EVEN
Enable error detection/correction (EDAC) on
instruction fetch only.
Enable error detection/correction (EDAC) on
operand (data) fetch only.
Enable parity detection function. (If both
EPR and either EEI or EED are enabled, EEI
or EED will take preference.)
Enable 1 wait state on MMU cache miss
cycle (1 = 1 WAIT, 0 = NO WAIT).
Enable protected write strobe (WR PROT
PIN).
1: WR PROT = write protected strobe
0: WR PROT = write protect level
(1 = write protect memory)
Enable block 1 of unimplemented memory
(as defined in unimplemented memory
register 1).
Enable block 2 of unimplementd memory (as
defined in unimplemented memory register
2).
Enable illegal PIO detection (as defined in
last implemented input and output registers,
and MIL-STD-1750A reserved I/O space).
Enable global memory protect (Set by
RESET, and reset by I/O command 4003).
Demultiplexed Address/data Bus in DMA
cycles.
Logical/Physical DMA (1 = LOGICAL, 0 =
Physical).
PACE 1757 M/ME
CONTROL REGISTER 1 (1F51)
(Default = C3FFH)
WA0/
WA1
SPI
PEG
IDL
Number of WAIT STATES on RDYA
Enable illegal PIO detection for MIL-
STD1750A spare I/O spaces.
Determines what is generated when both
EDAC and parity checks are disabled.
Enables/disables the genertion of an idle
cycle betwee BUS REQ and BUS GNT,
during read cycles, allowing for one
additional clock cycle to release the IB.
UNIMPLEMENTED MEMORY REGISTER 1 (1F55)
BL1 LO Low boundary of unimplemented block 1 of
memory.
BL1 HI High boundary of unimplemente block 1 of
memory.
UNIMPLEMENTED MEMORY REGISTER 2 (1F56)
BL2 LO Low boundary of unimplemented block 2 of
memory.
BL2 HI High boundary of unimplemented block 2 of
memory.
FIRST UNIMPLMENTED OUTPUT COMMAND
REGISTER (1F57)
BITS 0:5
BITS 6:15
Not used.
First unused sequential PIO output
command.
FIRST UNIMPLMENTED INPUT COMMAND
REGISTER (1F58)
BITS 0:5
BITS 0:6
Not used.
First unused sequential PIO input
command.
FIRST FAILING ADDRESS REGISTER (1F59)
PADR (4:19) 16 LSB of the physical address of the
first failure.
FIRST FAILING DATA REGISTER (1F5B)
BITS 0:15
"1" indicates the position of the wrong/
corrected bit in the data word.
MEMORY FAULT STATUS REGISTER (A00D)
LPA Page address within the group.
ID
Instruction/data
AS Group address.
Document # MICRO-10 REV B
Page 29 of 34