PACE1757M Datasheet, PDF (22/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM

PACE 1757 M/ME
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
CPU CLK
CPU clock
RESET
Reset
CON REQ
Console request
Description
A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty
cycle. This is a common input to all 3 devices.
An active LOW input that initializes the device. Input to the P1750A/AE,
P1753 and P1754.
An active LOW input that initiates console operations after completion of
the current instruction. Input to the CPU.
INTERRUPT INPUTS
Mnemonic
Name
PWRDN INT
Power down interrupt
USR₀INT -
USR₅INT
IOL₁INT -
IOL₂INT
User interrupt
I/O Level Interrupts
Description
An interrupt request input that cannot be masked or disabled. This signal
is active on the positive going edge or the high level, according to the
interrupt mode bit in the configuration register of the P1750A/AE.
Interrupt request input signals that are active on the positive going edge
edge or the high level, according to the interrupt mode bit in the configuration
register of the P1750A/AE.
Active HIGH interrupt requests that can be used to expand the number
of user interrupts. Inputs to the P1750A/AE interrupt register.
ERROR CONTROL
Mnemonic
Name
UNRCV ER
Unrecoverable error
MAJ ER
Major error
Description
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable. A signal from the CPU.
An active HIGH output that indicates the occurrence of an error classified
as major. A signal from the CPU.
DISCRETE CONTROL
Mnemonic
Name
NML PWRUP Normal power up
SNEW
TRIGO RST
Start new
Trigger-go reset
STRT ROM
Start Up Rom
DMA EN
Direct memory
Access enable
Description
An active HIGH output that is set when the CPU has successfully
completed the built-in self test in the initialization sequence. It can be reset
by the I/O command RNS.
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle. This signal is issued by the CPU.
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
An output follow the execution of the ESUR and DSUR, I/O commands as
defined in MIL-STD-1750A. It will be at the logical level "1" after executing
ESUR and at the logical "0" level after executing DSUR. Initially, it defaults
to a "1" on the P1754.
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
Document # MICRO-10 REV B
Page 22 of 34