PACE1757M Datasheet, PDF (26/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM

PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
STATUS BUS
Mnemonic
Name
Description
AK₀ - AK₃
Access key
Active HIGH outputs corresponding to the AK field of the processor status
word used to match the Access Lock in the MMU for memory accesses
(a mismatch will cause the MMU to pull the MEM PRT ER signal LOW),
and also indicate the processor state (PS). Priveledged instructions can
be executed with PS=0 only. These signals are tri-state for bus cycles not
assigned to this CPU
AS₀ - AS₃
Address state
Active HIGH outputs corresponding to the AS field of the processor status
word that selects the page register group in the MMU. In the DMA physical
demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant
bits of the physical address for use in the BPU function. These signals are
tri-state in bus cycles not assigned to this CPU.
INFORMATION BUS
Mnemonic
Name
IB₀ - IB₁₅
Information bus
EDC₀-EDC₅
Error Detection /
Correction Bus
A(0:1) /
EXT ADR(0:1)
A(2:15)
Address Bus
EXT ADR₀ -
EXT ADR₇
Extended Address
Bus
Description
A bi-directional time-multiplexed address/data BUS. IB₀ is the most
significant bit.
An active HIGH output BUS used for detection of errors on the data BUS
(IB₀-IB₁₅) and correction of single errors. When working in parity mode
EDC₀ is the parity bit. EDC₁-EDC₅ are undefined in this case.
An active HIGH output BUS from the PIC. Contains the address of the
current bus cycle as latched by the end of STRBA. In system configurations
including the MMU function, the only active lines during memory cycles
are A(4:15). In this example, A(2:3) are high impedance (don't care) and
A(0:1) turn into inputs called Extended Addresses, EXT AD (0:1). In this
situation, these two lines, supplied by the MMU, will be used to operate the
programmable ready generation during bus cycles.
A bi-directionaly active HIGH BUS. In CPU cycles, it is an output BUS
that is used to select one of 256 pages, 4K words each, expanding the
direct addressing space to 1M word. In DMA cycles, indicated by DMA-
ACK being active, it is also an output BUS except when programmed for
the physical demultiplexed DMA mode. In this example, it becomes an
input to receive the eight most significant bits of the DMA physical address
for use in the BPU function.
Document # MICRO-10 REV B
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