PACE1757M Datasheet, PDF (28/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM

PACE 1757 M/ME
COMBO REGISTER MAP
CONTROL REGISTER (1F50/9F50)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
QR1 QR2 QR3 QR4 ODD EEI EED EPR SPD WPT EB1 EB2 EIO GPT DMX DLP
CONTROL REGISTER 1 (1F51/9F51)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
WA0 WA1 SPI RES* PEG IDL
RESERVED
UNIMPLEMENTED MEMORY REGISTER 1 (1F55/9F55)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
BL1 LO
BL1 HI
UNIMPLEMENTED MEMORY REGISTER 2 (1F56/9F56)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
BL2 LO
BL2 HI
FIRST UNIMPLEMENTED OUTPUT COMMAND (1F57/9F57)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
X
X
X
X
X
X
LAST SEQUENTIAL PIO OUTPUT COMMAND
FIRST UNIMPLEMENTED INPUT COMMAND (1F58/9F58)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
X
X
X
X
X
X
LAST SEQUENTIAL PIO INPUT COMMAND
FIRST FAILING ADDRESS REGISTER (9F59)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
FIRST FAILING PHYSICAL ADDRESS - PADR (4:19)
FIRST FAILING DATA REGISTER (9F5A)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
FIRST FAILING DATA WORD
MEMORY FAULT STATUS REGISTER (A00D)
0
1
2
3
4
5
6
7
8
LPA
RESERVED
9 10 11 12 13 14 15
ID
AS
* Reserved
Document # MICRO-10 REV B
Page 28 of 34