PACE1757M Datasheet, PDF (17/34 Pages) Pyramid Semiconductor Corporation – COMPLETE EMBEDDED CPU SUBSYSTEM

MMU Cache Miss Cycle (WA = 0)
PACE 1757 M/ME
MMU Cache Miss Cycle (WA > 0)
* The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT GLAG. (See BPU Description). T = 1 Clock Period.
Note: All time measurements on active signals relate to 1.5V levels.
Document # MICRO-10 REV B
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