PE33241_14 Datasheet, PDF (7/19 Pages) Peregrine Semiconductor – UltraCMOS® Integer-N PLL Frequency Synthesizer

PE33241
Product Specification
Table 5. AC Characteristics @ 25°C, V_DD = 2.8V, unless otherwise noted (continued)
Symbol
Parameter
Condition
Min
Typical
Max
Unit
Single-sideband (SSB) phase noise 5/6 prescaler (F_IN = 3 GHz, P_FR = +5 dBm, f_c = 50 MHz, LBW = 500 kHz)⁵
_N
Phase noise
100 Hz offset
_N
Phase noise
1 kHz offset
_N
Phase noise
10 kHz offset
_N
Phase noise
100 kHz offset
SSB phase noise 10/11 prescaler (F_IN = 3 GHz, P_FR = +5 dBm, f_c = 50 MHz, LBW = 500 kHz)⁵
_N
Phase noise
100 Hz offset
_N
Phase noise
1 kHz offset
_N
Phase noise
10 kHz offset
_N
Phase noise
100 kHz offset
Phase noise figure of merit (FOM)⁵
-100
-109
-116
-118
-98
-104
-111
-117
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
FOM_flicker
Flicker figure of merit
5/6 prescaler
10/11 prescaler
-268
-263
dBc/Hz
dBc/Hz
FOM_floor
Floor figure of merit
5/6 prescaler
10/11 prescaler
-230
-229
dBc/Hz
dBc/Hz
FOM_flicker
FOM_floor
FOM_total, _N
PN_flicker = FOM_flicker + 20log (F_IN) - 10log (f_offset)
PN_floor = FOM_floor + 10log (f_c) + 20log (F_IN/f_c)
PN = 10log [10^(PNflick/10) + 10^(PNfloor/10)]
dBc/Hz
dBc/Hz
dBc/Hz
Notes:
1. fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification
2. 0 dBm minimum input power is recommended for improved phase noise performance when sine-wave is applied or a slew rate of 4V/ns minimum when using a
square wave
3. CMOS logic levels can be used to drive the reference input. If the VDD of the CMOS driver matches the VDD of the PLL IC, then the reference input can be DC
coupled. Otherwise, the reference input should be AC coupled. For sine-wave inputs, the minimum amplitude needs to be 0.5 Vpp. The maximum level should be
limited to prevent ESD diodes at the pin input from turning on. Diodes will turn on at one forward-bias diode drop above VDD or below GND. The DC voltage at the
Reference input is VDD/2
4. +2 dBm or higher reference power is recommended for improved phase noise performance when a sine-wave is applied or a slew rate of 0.5V/ns minimum
using a square wave
5. The phase noise can be separated into two normalized specifications: a floor figure of merit and a flicker figure of merit. To accurately measure the phase noise
floor without the contribution of the flicker noise, the loop bandwidth is set to 500 kHz and the phase noise is measured at a frequency offset near 100 kHz. The
flicker noise is measured at a frequency offset ≤ 1000 Hz. The formula assumes a -10 dB/decade slope versus frequency offset
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