PE33241_14 Datasheet, PDF (13/19 Pages) Peregrine Semiconductor – UltraCMOS® Integer-N PLL Frequency Synthesizer

PE33241
Product Specification
Figure 15. Serial Interface Mode Timing Diagram
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 8. Enhancement Register Bit Functionality
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit Function
Reserve**
Reserve**
f_p output
Power down
Counter load
MSEL output
f_c output
LD Disable
Description
Reserved
Reserved
Drives the M counter output onto the Dout output
Power down of all functions except programming interface
Immediate and continuous load of counter programming
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output
Drives the reference counter output onto the Dout output
Disables the LD pin for quieter operation
** Program to 0
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