PE33241_14 Datasheet, PDF (14/19 Pages) Peregrine Semiconductor – UltraCMOS® Integer-N PLL Frequency Synthesizer

Phase Detector
The phase detector is triggered by rising edges
from the main counter (f_p) and the reference
counter (f_c). It has two outputs, namely PD_U, and
PD_D . If the divided VCO leads the divided
reference in phase or frequency (f_p leads f_c),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (f_r leads
f_p), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between
the two input signals, f_p and f_c. The phase
detector gain is 400 mV/radian.
PD_U and PD_D are designed to drive an active
loop filter which controls the VCO tune voltage.
PD_U pulses result in an increase in VCO
frequency and PD_D results in a decrease in
VCO frequency.
PE33241
Product Specification
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2k ohm resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D. See Figure 14 for a
functional block diagram of this circuit.
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Document No. DOC-15014-4 │ UltraCMOS^® RFIC Solutions