PE33241_14 Datasheet, PDF (6/19 Pages) Peregrine Semiconductor – UltraCMOS® Integer-N PLL Frequency Synthesizer

PE33241
Product Specification
Table 5. AC Characteristics @ 25°C, V_DD = 2.8V, unless otherwise noted
Symbol
Parameter
Condition
Min
Control interface and latches (see Figures 14 and 15)
f_Clk
Serial data clock frequency¹
t_ClkH
Serial clock HIGH time
t_ClkL
Serial clock LOW time
t_DSU
SDATA set-up time after SCLK rising edge
t_DHLD
SDATA hold time after SCLK rising edge
t_PW
S_WR pulse width
t_CWR
SCLK rising edge to S_WR rising edge
t_CE
SCLK falling edge to E_WR transition
t_WRC
S_WR falling edge to SCLK rising edge
t_EC
E_WR transition to SCLK rising edge
t_MDO
MSEL data out delay after F_IN rising edge
Main divider 10/11 (including prescaler)
30
30
10
10
30
30
30
30
30
C_L = 12 pF
F_IN
Operating frequency
P_{F IN}
Input sensitivity
800
External AC coupling
800 MHz – < 4 GHz
4 GHz – 5 GHz
Main divider 5/6 (including prescaler)
F_IN
Operating frequency
P_{F IN}
Input sensitivity
800
External AC coupling
800 MHz – 4 GHz
Main divider (prescaler bypassed)
F_IN
Operating frequency
P_{F IN}
Input sensitivity
50
External AC coupling
50 MHz – 800 MHz
Reference divider
F_R
Operating frequency
P_FR
Reference input power³
Phase detector
Single-ended input
-5⁴
f_c
Comparison frequency
Typical
Max
10
8
5000
-10²
-5
-5²
0
4000
-10²
-5
800
-15²
-10
100
7
100
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
dBm
dBm
MHz
dBm
MHz
dBm
MHz
dBm
MHz
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 19
Document No. DOC-15014-4 │ UltraCMOS^® RFIC Solutions