PE33241_14 Datasheet, PDF (12/19 Pages) Peregrine Semiconductor – UltraCMOS® Integer-N PLL Frequency Synthesizer

PE33241
Product Specification
Serial Interface Mode
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (SDATA input), B₀
to B₂₀, is clocked serially into the primary register
on the rising edge of SCLK, MSB (B₀) first. The
contents from the primary register are transferred
into the secondary register on the rising edge of
S_WR according to the timing diagram shown in
Figure 15. Data is transferred to the counters as
shown in Table 6.
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (SDATA input), B₀
to B₇, is clocked serially into the enhancement
register on the rising edge of SCLK, MSB (B₀)
first. The enhancement register is double buffered
to prevent inadvertent control changes during serial
loading, with buffer capture of the serially-entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure 15.
After the falling edge of E_WR, the data provides
control bits as shown in Table 7 with bit functionality
enabled by asserting the ENH input “low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Direct input “high”.
Counter control bits are set directly at the pins as
shown in Table 6 and Table 7.
Table 6. Primary Register Programming
Interface
Mode
ENH
R5 R4 M8 M7 _{Pre_En} M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3
A2
A1
A0 ADDR
Serial *
1
B0 B1 B2 B3
B4
B5
B6
B7
B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
B20
Direct
1
R5 R4 M8 M7
Pre_En
M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0
A3
A2
A1
A0
0
* Serial data clocked serially on SCLK rising edge while E_WR “low” and captured in secondary register on S_WR rising edge
MSB (first in)
(last in) LSB
Table 7. Enhancement Register Programming
Interface
Mode
ENH
Direct
Reserved
Reserved
fp output
Power
Down
Counter
load
MSEL
output
Serial*
0
0
B0
B1
B2
B3
B4
B5
* Serial data clocked serially on SCLK rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
fc output
B6
LD Disable
B7
(last in) LSB
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 19
Document No. DOC-15014-4 │ UltraCMOS^® RFIC Solutions