EQ2660-9R Datasheet, PDF (13/26 Pages) Power-One – Q Series Data Sheet 66 – 132 Watt DC-DC Converters

Q Series Data Sheet
®
66 – 132 Watt DC-DC Converters
Redundant Configuration
Fig. 10a shows a circuit with ORing diodes D_R in the positive
output lines, forming a redundant configuration. For accurate
output voltage regulation, the sense lines are connected after
the ORing diodes. The T pins should be connected together to
+
05091b
T
R_p
Vo+/Vo1+
D_R
Out OK+
S+
Out OK–
S–
i
Vo–/Vo1–
Vi+ Vo+/Vo2+
Vi– Vo–/Vo2–
T
D_R
Vo+/Vo1+
Out OK+
S+
Out OK–
S–
i
Vo–/Vo1–
Vi+ Vo+/Vo2+
–+
Vi– Vo–/Vo2–
i
Fig. 10a
Simple redundant configuration of double-output models with
parallel-connected outputs.
+
R_p
06097b
T
Vo+/Vo1+
Out OK+
S+
Out OK–
S–
i
Vo–/Vo1–
Vi+ Vo+/Vo2+
Vi– Vo–/Vo2–
D_R
D_S
R_S
T
D_R
Vo+/Vo1+
Out OK+
S+ ^DS
Out OK–
R_S
S–
i
Vo–/Vo1–
Vi+ Vo+/Vo2+
–+
Vi– Vo–/Vo2–
i
Fig. 10b
Redundant configuration of double-output models with
parallel-connected outputs.
produce reasonable current sharing between the parallel-
connected converters.
If one of the converters fails, the remaining converters can
deliver the whole output power.
Note: The current-share logic can only increase the output voltage
marginally and remains functional even in the case of a failing
converter.
Fig. 10b shows a quite similar circuit with ORing diodes D_R, but
with different output loads. To compensate for the voltage drop
of the ORing diodes (if necessary), an auxiliary circuit is added
to each power supply consisting of a small diode D_S and a
small resistor R_S. We recommend a current of approximately 10
mA through D_S and R_S. Only Load 0 benefits from a secured
supply voltage.
The current sharing may be improved by interconnecting the T
pins of the converters. This circuit is a bit less accurate, but
more flexible and less sensitive.
Caution: Do not connect the sense lines after the ORing diodes,
but directly with the respective outputs. If for some reason one of
the converters switches off and the ORing diode is blocking, a
reverse voltage can appear between the sense pin and the
respective output pin and damage the converter.
Output Voltage Regulation
The dynamic load regulation is shown in the figure below.
V_o
V_od
V_o ±1 %
V_o ±1 %
V_od
t_d
t_d
t
I_o/I_{o nom}
1
0.5
≥ 10 µs
0
≥ 10 µs
Fig. 11
Deviation of V_o versus dynamic load change
05102c ^t
The static load regulation measured at the sense pins is
negligible. Correct connection of the sense lines almost
eliminates any load regulation; see Sense Lines.
In a symmetrical configuration the output 1 with open R input is
regulated to V_{o1 nom}, regardless of the output currents. If the
load on output 2 is too small (<10% of I_{o nom}), its voltage will
rise and may activate the overvoltage protection, which will
then reduce the voltage on both outputs.
V_o2 depends upon the load distribution: If each output is loaded
with at least 10% of I_{o nom}, the deviation of V_o2 remains within
±5% of V_{o nom}. The following figures explain the regulation with
different load distributions up to the current limit. If I_o1 = I_o2 or
the two outputs are connected in series, the deviation of V_o2
remains within ±1% of the value of V_{o nom}, provided that the
load is at least I_{o min}.
BCD20011- G Rev AG, 12-Mar-2012
Page 13 of 26
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