PM5316 Datasheet, PDF (85/491 Pages) PMC-Sierra, Inc – Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner

SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)
Production
The FIFO read and write Addresses are monitored. Pointer justification requests will be made to
the Pointer Generator based on the proximity of the Addresses relative to programmable
thresholds. The Pointer Generator schedules a pointer increment event if the FIFO depth is below
the lower threshold and a pointer decrement event if the depth is above the upper threshold. FIFO
underflow and overflow events are detected and path AIS is optionally inserted in the Drop bus
for three frames to alert downstream elements of data corruption.
Pointer Generator
The Pointer Generator generates the Drop bus pointer (H1, H2) as specified in the references. The
pointer value is used to determine the location of the path overhead (the J1 byte) in the Drop bus
STS-1 (STM-0/AU-3) stream. The algorithm can be modeled by a finite state machine. Within the
pointer generator algorithm, five states are defined as shown below:
• NORM_state (NORM).
• AIS_state (AIS).
• NDF_state (NDF).
• INC_state (INC).
• DEC_state (DEC).
The transition from the NORM to the INC, DEC, and NDF states is initiated by events in the
Elastic Store (ES) block. The transition to/from the AIS state are controlled by the pointer
interpreter (PI) in the Receive Path Overhead Processor block. The transitions from INC, DEC,
and NDF states to the NORM state occur autonomously with the generation of special pointer
patterns.
Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use
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Document ID: PMC-1990822, Issue 4