PM5316 Datasheet, PDF (37/491 Pages) PMC-Sierra, Inc – Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner

SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)
Production
Pin Name
RCLK1
RCLK2
RCLK3
RCLK4
PGMRCLK
Type
Output
Output
PGMTCLK
Output
CP1
CN1
CP2
CN2
CP3
CN3
CP4
CN4
PECLV
Analog
Input
Pin
Function
No.
C7
The Receive Clock (RCLK1-4) signal provides a timing reference for
D7
the SPECTRA-4x155 receive line interface outputs. The signal is
B6
nominally 19.44 MHz. It is a divide-by-eight of the recovered clock.
E7
When not used, RCLK1-4 can be held low using the RCLKEN bit in
the SPECTRA-4x155 Clock Control register.
D6
The programmable receive clock (PGMRCLK) signal provides timing
reference for the receive line interface.
PGMRCLK is a divided version of one of the RCLK clocks. The
PGMRCHSEL bits of the Master Clock Control register are used to
select which of the four clocks is the source for PRGMRCLK. When
the PGMRCLKSEL bit of the Master Clock Control register is set low,
PGMRCLK is a nominal 19.44 MHz, 40-60% duty cycle clock. When
PGMRCLKSEL register bit is set to high, PGMRCLK is a nominal 8
KHz, 40-60% duty cycle clock.
PGMRCLK output can be disabled and held low by programming the
PGMRCLKEN bit in the Master Clock Control register.
E6
The programmable transmit clock (PGMTCLK) signal provides timing
reference for the transmit line interface.
PGMTCLK is a divided version of the TCLK clock. When the
PGMTCLKSEL register bit is set low, PGMTCLK is a nominal 19.44
MHz, 40-60% duty cycle clock. When the PGMTCLKSEL bit of the
Master Clock Control register is set high, PGMTCLK is a nominal 8
KHz, 40-60% duty cycle clock.
PGMTCLK output can be disabled and held low by programming the
PGMTCLKEN bit in the Master Clock Control register.
G2
The analog CP1-4 and CN1-4 pins are provided for applications that
G3
must meet SONET/SDH jitter transfer specifications. A 220 nF X7R
N3
10% ceramic capacitor can be attached across each CP1-4 and
N2
CN1-4 pair.
U3
U2
AD2
AD3
D2
The PECL receiver input voltage (PECLV) pin configures the PECL
receiver level shifter. When PECLV is set to logic zero, the PECL
receivers are configured to operate with a 3.3V input voltage. When
PECLV is set to logic one, the PECL receivers are configured to
operate with a 5.0 V input voltage.
Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use
18
Document ID: PMC-1990822, Issue 4