PM5316 Datasheet, PDF (440/491 Pages) PMC-Sierra, Inc – Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner

SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)
Production
13.15 Clock Recovery
Figure 24 is an abstraction of the clock recovery PLL illustrating the connections to external
components. In order to meet jitter transfer requirements for WAN applications, the CRU requires
an external 220nF X7R 10% ceramic loop capacitor. This capacitor is placed across pins C1 and
C2 in close proximity to the chip pins.
The external loop filter capacitor is used as a floating capacitor which means that neither of C1
and C2 is grounded.
Figure 24 Clock Recovery External Components
RXD+/
RE-FCLK
Phase
Detector
Charge
Pump
Differential Loop Filter
VCO
Recovered Clock
On-Chip Circuitry
Off-Chip Circuitry
CN
220nF
CP
Please refer to the SPECTRA-4X155 reference design (PMC-1991245) for further
recommendations.
Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use
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Document ID: PMC-1990822, Issue 4