PM5316 Datasheet, PDF (379/491 Pages) PMC-Sierra, Inc – Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner

SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)
Production
Registers 11E5H, 12E5H, 13E5H, 14E5H, 15E5H, 16E5H, 17E5H, 18E5H, 19E5H, 1AE5H,
1BE5H, 1CE5H: TPIP Pointer LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PTR[7]
PTR[6]
PTR[5]
PTR[4]
PTR[3]
PTR[2]
PTR[1]
PTR[0]
Default
X
X
X
X
X
X
X
X
The register reports the lower eight bits of the active offset.
PTR[7:0]
The PTR[7:0] bits contain the eight LSBs of the active offset value as derived from the H1
and H2 bytes. To ensure reading a valid pointer, the NDFI, NSEI and PSEI bits of the TPIP
Pointer Interrupt Status register should be read before and after reading this register to ensure
that the pointer value did not changed during the register read.
Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use
360
Document ID: PMC-1990822, Issue 4