PM5342 Datasheet, PDF (520/558 Pages) PMC-Sierra, Inc – SONET/SDH Payload Extractor/Aligner

DATA SHEET
PMC-970133
ISSUE 4
PM5342 SPECTRA-155
SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 80 - Microprocessor Interface Write Access Timing (Motorola
Mode)
A[9:0]
RWB
tS_AW
Valid Address
tS _RWB
tH _RWB
ALE
(CSB & E)
D[7:0]
tS_ALW
tV_L
tS_LW
tH _ALW
tH_LW
tV_WR
tH_AW
tS _DW
tH _DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. In Intel mode, a valid write cycle is defined as a logical OR of the CSB and
the WRB signals.
2. In Motorola mode, a valid write cycle is defined as a logical AND of the E
signal, the inverted RWB signal and the inverted CSB signal.
3. Microprocessor timing applies to normal mode register accesses only.
4. In non-multiplexed address/data bus architectures, ALE should be held high,
parameters tS_ALW, tH_ALW, tV_L, and tS_LW are not applicable.
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