PM5342 Datasheet, PDF (424/558 Pages) PMC-Sierra, Inc – SONET/SDH Payload Extractor/Aligner

DATA SHEET
PMC-970133
ISSUE 4
PM5342 SPECTRA-155
SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
PER5:
The receive trace identifier persistence bit (PER5) control the number of
times a path trace identifier message must be received unchanged before
being accepted. When PER5 is set high, a message is accepted when it is
received unchanged five times consecutively. When PER5 is set low, the
message is accepted after three identical repetitions.
RTIMIE:
The receive path trace identifier message mismatch interrupt enable bit
(RTIMIE) controls the activation of the interrupt output when the comparison
between accepted identifier message and the expected message changes
state from match to mismatch and vice versa. When RTIMIE is set high,
changes in match state activates the interrupt (INTB) output. When RTIMIE
is set low, path trace identifier message state changes will not affect INTB.
RTIUIE:
The receive path trace identifier message unstable interrupt enable bit
(RTIUIE) controls the activation of the interrupt output when the receive
identifier message state changes from stable to unstable and vice versa. The
unstable state is entered when the current identifier message differs from the
previous message for eight messages. The stable state is entered when the
same identifier message is received for three or five consecutive messages
as controlled by the PER5 bit. When RTIUIE is set high, changes in the
received path trace identifier message stable/unstable state of will activate
the interrupt (INTB) output. When RTIUIE is set low, path trace identifier
state changes will not affect INTB.
RRAMACC:
The receive RAM access control bit (RRAMACC) directs read and writes
access to between the receive and transmit portion of the SPECTRA-155.
When RRAMACC is set high, subsequent microprocessor read and write
accesses are directed to the receive side trace buffers. When RRAMACC is
set low, microprocessor accesses are directed to the transmit side trace
buffer.
ZEROEN:
The zero enable bit (ZEROEN) enables TIM assertion and removal based on
an all ZEROs path trace message string. When ZEROEN is set high, all
ZEROs path trace message strings are considered when entering and exiting
TIM states. When ZEROEN is set low, all ZEROs path trace message strings
are ignored. TIU assertion and removal are not affected by setting this
register bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 402