PM5342 Datasheet, PDF (51/558 Pages) PMC-Sierra, Inc – SONET/SDH Payload Extractor/Aligner

DATA SHEET
PMC-970133
ISSUE 4
PM5342 SPECTRA-155
SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin
Name
RCLK
RXC
RFP
Pin
PIN
Type No.
Output L17
Output L20
Tristate M20
Output
Function
The receive clock (RCLK) output provides a timing
reference for the SPECTRA-155 receive line
interface outputs. For STS-3/3c (STM-
1/AU3/AU4) operation, RCLK is nominally 19.44
MHz. For STS-1 (STM-0/AU3) RCLK is nominally
6.48. RCLK is a divide by eight of the recovered
clock or the RRCLK+/- inputs as determined using
the RBYP input signal.
When not used, RCLK can be held low using the
RCLKEN bit in the SPECTRA-155 Clock Control
register.
The receive clock (RXC) output provides a 51.84
MHz timing reference. RXC is a 51.84 MHz,
nominally 50% duty cycle clock. For STS-3/3c
(STM-1/AU3/AU4) mode, RXC is a divide by three
of the recovered clock or the RRCLK+/- inputs as
determined using the RBYP input signal. For
STS-1 (STM-0/AU3) mode, RXC is the recovered
clock or the RRCLK+/- inputs as determined using
the RBYP input signal.
When not used, RXC can be held low using the
RXCEN bit in the SPECTRA-155 Clock Control
register.
The receive frame pulse (RFP) output is an 8 KHz
signal derived from the receive line clock. RFP is
pulsed high for one RCLK cycle every 2430 RCLK
cycles for STS-3c (STM-1/AU4) or every 810
RCLK cycles for STS-1 (STM-0/AU3). A single
discontinuity in RFP position occurs if a change of
frame alignment occurs.
RFP can be tristated using the TRIS_OHB input
and the ROH_TS bit in the SPECTRA-155
Receive Overhead Output Control register. On
reset, RFP will be tristate if TRIS_OHB is low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 29