TDA6650TT Datasheet, PDF (9/55 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
8.1 Write mode; R/W = 0
After the address transmission (first byte), data bytes can
be sent to the device (see Table 3). Five data bytes are
needed to fully program the TDA6650TT; TDA6651TT.
The I²C-bus transceiver has an auto-increment facility that
permits programming the device within one single
transmission (address + 5 data bytes).
The TDA6650TT; TDA6651TT can also be partly
programmed on the condition that the first data byte
following the address is byte 2 (divider byte 1) or byte 4
(control byte 1). The first bit of the first data byte
transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I²C-bus STOP condition is
sent by the controller, additional data bytes can be entered
without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission
(STOP condition). Each control byte is loaded after the
8th clock pulse of the corresponding control byte. Main
divider data are valid only if no new I²C-bus transmission
is started (START condition) during the computation
period of 50 µs.
Both DB1 and DB2 need to be sent to change the main
divider ratio. If the value of the ratio selection bits R2, R1
and R0 are changed, the bytes DB1 and DB2 have to be
sent in the same transmission.
handbook, full pagewidth
START
ADDRESS
BYTE
DIVIDER
BYTE 1
DIVIDER
BYTE 2
CONTROL CONTROL CONTROL CONTROL
BYTE 1 BYTE 2 BYTE 1 BYTE 2
STOP
I²C transmission dedicated to
the MOPLL
50 µs
START
ADDRESS
BYTE
I²C transmission
dedicated to
another IC
FCE921
Fig.4 Example of I²C-bus transmission frame.
Table 3 I²C-bus write data format
NAME
BYTE
MSB⁽¹⁾
Address byte
1
1
1
0
Divider byte 1 (DB1) 2
0
N14 N13
Divider byte 2 (DB2) 3
N7
N6
N5
Control byte 1
4
(CB1); see Table 4
1 T/A = 1 T2
1 T/A = 0 0
Control byte 2 (CB2) 5
CP2 CP1 CP0
Note
1. MSB is transmitted first.
BIT
0
0
N12 N11
N4
N3
T1
T0
0
ATC
BS5 BS4
MA1
N10
N2
R2
AL2
BS3
MA0
N9
N1
R1
AL1
BS2
LSB
R/W = 0
N8
N0
R0
AL0
BS1
ACK
A
A
A
A
A
A
2004 Mar 22
9