TDA6650TT Datasheet, PDF (4/55 Pages) NXP Semiconductors – 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)

Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
3 GENERAL DESCRIPTION
The TDA6650TT; TDA6651TT is a programmable 3-band
mixer/oscillator and low phase noise PLL synthesizer
intended for pure 3-band tuner concepts applied to hybrid
(digital and analog) terrestrial and cable TV reception.
The device includes three double balanced mixers for low,
mid and high bands, three oscillators for the corresponding
bands, a switchable IF amplifier, a wide band AGC
detector and a low noise PLL synthesizer. The frequencies
of the three bands are shown in Table 1. Two pins are
available between the mixer output and the IF amplifier
input to enable IF filtering for improved signal handling and
to improve the adjacent channel rejection.
Table 1 Recommended band limits in MHz for PAL and
DVB-T tuners; note 1
BAND
Low
Mid
High
RF INPUT
MIN.
44.25
157.25
443.25
MAX.
157.25
443.25
863.25
OSCILLATOR
MIN.
83.15
196.15
482.15
MAX.
196.15
482.15
902.15
Note
1. RF input frequency is the frequency of the
corresponding picture carrier for analog standard.
The IF amplifier is switchable in order to drive both
symmetrical and asymmetrical outputs. When it is used as
an asymmetrical amplifier, the IFOUTB pin needs to be
connected to the supply voltage V_CCA.
Five open-drain PMOS ports are included on the IC. Two
of them, BS1 and BS2, are also dedicated to the selection
of the low, mid and high bands. PMOS port BS5 pin is
shared with the ADC.
The AGC detector provides a control that can be used in a
tuner to set the gain of the RF stage. Six AGC take-over
points are available by software. Two programmable AGC
time constants are available for search tuning and normal
tuner operation.
The local oscillator signal is fed to the fractional-N divider.
The divided frequency is compared to the comparison
frequency into the fast phase detector which drives the
charge pump. The loop amplifier is also on-chip, including
the high-voltage transistor to drive directly the 33 V tuning
voltage without the need to add an external transistor.
The comparison frequency is obtained from an on-chip
crystal oscillator. The crystal frequency can be output to
the XTOUT pin to drive the clock input of a digital
demodulation IC.
Control data is entered via the I²C-bus; six serial bytes are
required to address the device, select the local
oscillator (LO) frequency, select the step frequency,
program the output ports and set the charge pump current
or select the ALBC mode, enable or disable the crystal
output buffer, select the AGC take-over point and time
constant and/or select a specific test mode. A status byte
concerning the AGC level detector and the ADC voltage
can be read out on the SDA line during a read operation.
During a read operation, the loop ‘in-lock’ flag, the
Power-on reset flag and the automatic loop bandwidth
control flag are read.
The device has 4 programmable addresses. Each address
can be selected by applying a specific voltage to pin AS,
enabling the use of multiple devices in the same system.
The I²C-bus is fast mode compatible, except for the timing
as described in the functional description and is
compatible with 5, 3.3 and 2.5 V microcontrollers
depending on the voltage applied to pin BVS.
4 ORDERING INFORMATION
TYPE
NUMBER
TDA6650TT
TDA6651TT
PACKAGE
NAME
DESCRIPTION
TSSOP38 plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
VERSION
SOT510-1
2004 Mar 22
4